Charge coupled devices (CCD's) are used in various fields such as solid state imaging, analog signal processing, analog delay lines and memories for analog and digital signals. In the process of transferring signals either to or from the cells of the CCD, the CCD presents a capacitive load to clock drivers. Transferrng signals in the form of charge packets from one location to the next of a CCD or from a CCD to an external processing circuit is called charge transfer. The efficiency with which a charge packet is transferred is referred to in the art as "charge transfer efficiency." In order to have effective use of such CCD's, the charge transfer efficiency should be as high as possible.
The signal, in form of a charge packet, is transferred from one location to another by the application of an input pulse through a clock driver circuit. The function of the clock driver circuit is to provide a signal to the CCD at various required voltage levels with proper rise and fall times. Each cell has a certain capacitance. The total capacitive load presented to a clock driver circuit is linearly proportional to the number of cells. CCD's are often used for video applications. Typically charge packets are clocked out line by line every 63.5 .mu.s (line rate) and clocked out pixel by pixel at the pixel rate which depends upon the number of pixels in each line. The clock driver circuits used for CCD's are generally divided into two types, namely a vertical clock driver circuit and a horizontal clock driver circuit. Each of these circuits normally has two phases. Each place drives a different channel that is 180.degree. apart from the other channel. That is the first channel is at a high level while the second channel is at a low level and vice versa. The vertical clock drivers see many more cells and hence a relatively high capacitive load during transfer. The rate of transfer is at a low frequency. The horizontal clock drivers see a much lower capacitance (fewer cells) in the order of 50 to 100 pF.
A problem is to clock out the entire CCD at a rate often of 10 MHz or higher. At such frequencies the load seen by the clock drivers can be in the order of 5,000 to 10,000 pF or even more. Such a capacitive load requires 10 or more amperes of current with a 2 amp/ns rise and fall time. In addition, the fast rise and fall times are particularly necessary for high speed operation of CCD's used in electronic imaging.
A conventional prior art driver circuit for a high speed CCD is shown in FIG. 1. Two switching transistors, Q.sub.1 and Q.sub.2, are connected, in series. At the junction of these transistors, an output current is provided which charges a capacitive load. The capacitor C represents the capacitive load of the CCD. Coupling capacitors C.sub.1 and C.sub.2, in response to the input signal are charged and discharged to cause transistors Q.sub.1 and Q.sub.2 to be alternately switched ON and OFF. Diodes D.sub.1 and D.sub.2 are used to perform charging and discharging of the coupling capacitors C.sub.1 and C.sub.2 and thereby prevent transistors Q.sub.1 and Q.sub.2 from being damaged. In operation when transistor Q.sub.1 is ON, transistor Q.sub.2 is OFF and then capacitor C is charged. When the transistor Q.sub.1 is turned OFF and transistor Q.sub.2 is turned on, capacitor C discharges through the transistor Q.sub.2 to ground. This circuit was actually tested using very fast switching transistors and was only able to drive a maximum load of about 1,000 pF at 10 MHz.
In order to appreciate the present invention, it will be helpful to briefly analyze the characteristics of capacitive loads. FIG. 2A depicts a constant current source I.sub.S for charging a capacitor C. At time t=t.sub.0, the switch S is closed and the charging cycle begins. The voltage across the capacitor C is given by: ##EQU1##
The current is given by the well known formula: ##EQU2## To charge the capacitor C to 5 volts in 5 nS, the current I.sub.S required is tabulated in Table I.
TABLE I ______________________________________ C in pf i.sub.S in Amps ______________________________________ 100 0.1 1,000 1 5,000 5 10,000 10 ______________________________________
Referring to FIG. 2B, which is a model of a constant voltage source for charging a capacitor C, the voltages across the capacitor after the switch is closed, is given by (where V.sub.0 =0): ##EQU3## where i is the instantaneous current. Solving this differential equation one obtains: EQU i=V.sub.S /R.sub.s .multidot.e.sup.-t/R S.sup.C ( 3)
The current i at the time the switch S is closed (t=0) is given by V.sub.S /R.sub.S. Clearly from equation 3 at time t=0, with R.sub.s =0, the current i is infinite. Thus at the time t=0, the capacitor C acts as a short circuit. Consequently, the switch S can be damaged without protection. For any solid state switch to charge a capacitor, it needs short circuit protection. Many devices which have been developed to drive capacitive loads, work without protection because the "on" resistance of the transistor, although small, protects it for short duration spikes. To drive high capacitive loads at high frequencies, the switch should have very little propogation delay and a high current capability. There are no switching transistors which presently can fulfill both these conditions. For a specific example, if as shown in FIG. 3, a switching transistor can drive a maximum of 100 mA without damage to itself, then for a supply of 5 volts, a 50 ohms resistor in series with the switching transistor will provide short circuit protection in accordance within equality (4): ##EQU4## where i.sub.max is the absolute maximum collector current of transistor.
By paralleling a plurality of transistors shown in FIG. 3, the total charging current going into any capacitor can be equal to the sum currents drawn by each transistor. This arrangement is not practical to use in operating a CCD since it provides no ready means to discharge the capacitor.
The CCD clock driver circuit shown in FIG. 1 can be schematically represented as shown in FIG. 4. Shown there are two separate switches S.sub.1 and S.sub.2 which, of course, may be embodied by switching transistors Q.sub.1 and Q.sub.2. When switch S.sub.1 is closed, the CCD receives charging current and eventually reaches the upper supply voltage +V with the time constant of RC. When S.sub.1 is open and S.sub.2 is closed, the CCD will discharge through the switch S.sub.2 and reach the lower supply voltage -V. Switches S.sub.1 and S.sub.2 are complementary and should not be on at the same time. Failure of these switching transistors at high frequencies for large capacitive loads is a problem that has been solved by the present invention.